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fn8888 rev. 3.00 page 1 of 48 feb 8, 2018 fn8888 rev. 3.00 feb 8, 2018 ISL68144 digital dual output, 4-phase con figurable, pwm controller with pmbus for cavium datasheet the ISL68144 is a digital dual output, flexible multiphase (x+y 4) pwm controller developed to support the latest cavium cn99xx server cla ss processors. the ISL68144 supports the pmbus 1.3 specificat ion and is designed to meet the latest intel server-c lass transient performance specifications. either output ca n be configured to support any desired phase assignments up to a maximum of four phases across the two outputs (x+y), such as 3+1, 2+2, 2+1, or even a single output operation as a 4+0 configuration. with full digital control, this new generation of controllers ushers in design flexibility by supporting any mi croprocessor, fpga, or digital asic rail requirements that include adjustable load setting. the ISL68144 uses proprietary re nesas linear synthetic digital current modulation scheme to achieve the industry?s best combination of transient respon se and ease of tuning while addressing the challenges of modern multiphase designs. device configuration and telemetry monitoring is accomplished using the intuitive renesas powernavigator? software. the ISL68144 device supports on-chip, nonvolatile memory to store various conf iguration settings that are user-selectable through pin-strap, giving system designers increased power density to configure and deploy multiple configurations. the device supports an automatic phase add/drop feature to allow maximum efficiency across all load ranges. thresholds for automatic phase add/drop are user-programmable using powernavigator. the ISL68144 supports a comprehensive fault management system to enable the design of highly reliable systems. from a multitiered overcurrent protection scheme to the configurable power-good and output over voltage/undervoltage fault thresholds and temperature moni toring, almost any need is accommodated. with minimal external components, easy configuration, robust fault management, and highly accurate regulation capability, implementing a high-performance, multiphase regulator has never been easier. applications ? networking equipment ? telecom and datacom equipment ? server and storage equipment ? point-of-load power supply (memory, dsp, asic, fpga) features ? advanced linear digital modulation scheme - zero latency synthetic current control for excellent hf current balance - dual-edge modulation for fastest transient response ? auto phase add/drop for excellent load vs efficiency profile ? pmbus 1.3 support - telemetry - v in , v out , i out , power in/out, temperature, and various fault status registers - up to 2mhz bus interface ? flexible phase configuration - 4+0, 3+1, 2+2 phase operation - operation using less than four phases between two outputs is also supported ? diode braking for overshoot reduction ? differential remote voltage sensing supports ? 0.5% closed loop system accuracy over load, line, and temperature ? highly accurate current sensing for excellent load line regulation and accurate ocp - supports isl99227 60a smart power stages - supports dcr sense with integrated temperature compensation ? comprehensive fault management enables high reliability systems - pulse-by-pulse phase current limiting - total output current protection - output and input ov/uv - open voltage sense detect - black box recording capability for faults ? intuitive configuration using powernavigator - nvm to store up to eight configurations ? pb-free (rohs compliant) related literature ? for a full list of related documents, visit our website - ISL68144 product page
ISL68144 fn8888 rev. 3.00 page 2 of 48 feb 8, 2018 table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 driver, drmos, and smart power stage recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical application: 3+1 configuration with isl99227 sps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical application: 2+2 configuration with isl99227 sps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical application: 2+2 configuration with dcr sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pwm modulation scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pmbus address selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 phase configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 automatic phase add and drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output voltage configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 temperature sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 lossless input current and power sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 current feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 soft-start delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 stored configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 fault monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-good signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output current protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 smart power stage oc fault detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 thermal monitoring (twarn) and pr otection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 layout and design considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 pmbus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pmbus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pmbus command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pmbus use guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 pmbus data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 pmbus command detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ISL68144 fn8888 rev. 3.00 page 3 of 48 feb 8, 2018 ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL68144iraz ISL68144 irz -40 to +85 40 ld 5x5 tqfn l40.5x5d notes: 1. add ?-t? suffix for 6k unit or ?-t7a? suffix for 250 unit tape and reel options. refer to tb347 for details on reel specifications. 2. these pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). pb -free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), see the product information page for ISL68144 . for more information on msl, see tb363 . table 1. key differences between family of parts part number phase configuration output x/output y specification supported package isl68147 x+y 7 pmbus qfn 48 ld, 6x6mm ISL68144 x+y 4 pmbus tqfn 40 ld, 5x5mm isl68137 x+y 7 pmbus/avsbus qfn 48 ld, 6x6mm isl68134 x+y 4 pmbus/avsbus tqfn 40 ld, 5x5mm isl68127 x+y 7 pmbus qfn 48 ld, 6x6mm isl68124 x+y 4 pmbus tqfn 40 ld, 5x5mm pin configuration ISL68144 (40 ld tqfn) top view 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 dnc dnc dnc sa vccs vcc tmon1 tmon0 vsen0 rgnd0 cs0 csrtn0 cs1 csrtn1 cs2 csrtn2 cs3 csrtn3 rgnd1 vsen1 pwm0 pwm1 pwm2 pwm3 gnd dnc gnd dnc dnc dnc en0 en1 twarn pg0 pg1 scl sda salrt config vinsen epad (gnd)
ISL68144 fn8888 rev. 3.00 page 4 of 48 feb 8, 2018 functional pin descriptions refer to table 4 on page 19 for design layout considerations. pin number pin name description 4, 3, 2, 1 pwm[3:0] pulse-width modulation (pwm) outputs. connect these pins to the pwm input pins of 3.3v logic-compatible, renesas smart power stages, driver ic(s), or power stages. 5, 7 gnd ground pins. connect directly to system gnd plane. 6, 8, 9, 10, 38, 39, 40 dnc do not connect any signals to these pins. 11 en0 input pin used for enable control of output 0. active high. connect to ground if not used. 12 en1 input pin used for enable control of output 1. active high. connect to ground if not used. 13 twarn thermal warning flag. this open-drain output will be pulled low in the event of a sensed over-temperature at tmon pins without disabling the outputs. maximum pull-up voltage is v cc . 14 pg0 open-drain, power-good indicator for output 0. maximum pull-up voltage is v cc . 15 pg1 open-drain, power-good indicator for output 1. maximum pull-up voltage is v cc . 16 scl serial clock signal pin for smbus interface. maximum pull-up voltage is v cc . 17 sda serial data signal pin for smbus interface. maximum pull-up voltage is v cc . 18 salrt serial alert signal pin for smbus interface. maximum pull-up voltage is v cc . 19 config configuration id selection pin. see table 3 on page 16 for more details. 20 vinsen input voltage sense pin. connect to vin through a resist or divider (typically 40.2k/10k) with a 10nf decoupling capacitor. 21 vsen1 positive differential voltage sense input for output 1. connect to positive remote sensing point. connect to ground if not used. 22 rgnd1 negative differential voltage sense input for output 1. connect to negative remote sensing point. connect to ground if not used. 23, 25, 27, 29 csrtn[3:0] the cs and csrtn pins are current sense in puts to individual phase differential amplifiers. unused phas es should have their respective current sense inputs grounded. the ISL68144 supports smart power stage, dcr, and resistor sensing. connection details depend on the current sense method chosen. 24, 26, 28, 30 cs[3:0] 31 rgnd0 negative differential voltage sense input for output 0. connect to negative remote sensing point. connect to ground if not used. 32 vsen0 positive differential voltage sense input for output 0. connect to positive remote sensing point. connect to ground if not used. 33 tmon0 input pin for external temperature measurement at ou tput 0. supports diode based temperature sensing as well as smart power stage sensing. refer to ? temperature compensation ? on page 14 for more information. 34 tmon1 input pin for external temperature measurement at ou tput 1. supports diode based temperature sensing as well as smart power stage sensing. refer to ? temperature compensation ? on page 14 for more information. 35 vcc chip primary bias input. connect this pin directly to a +3.3v supply with a high quality mlcc bypass capacitor. 36 vccs internally generated 1.2v ldo logic supply from vcc. decouple with 4.7f or greater mlcc (x5r or better). 37 sa pmbus address selection pin. see table 2 for more details. epad gnd package pad serves as gnd return for all chip functi ons. connect directly to system gnd plane with multiple thermal vias. driver, drmos, and smart power stage recommendations renesas part number quiescent current (ma) gate drive voltage (v) number of drivers comments isl99227 4.85 5 single 60a, 5x5 smart power stage isl99140 0.19 5 single 40a, 6x6 drmos isl6596 0.19 5 single connect isl6596 vctrl to 3.3v
ISL68144 fn8888 rev. 3.00 page 5 of 48 feb 8, 2018 internal block diagram figure 1. internal block diagram isum-0 vsa adc vdroop pid isum-1 adc cycle- cycle ocp adc cycle- cycle ocp adc cycle- cycle ocp adc cycle- cycle ocp summed ocp current ac fb vsa adc vdroop pid current ac fb summed ocp adc fault and telemetry manager pmbus interface status manager cpu nvm ov uv + - + - ov uv + - + - loop manager phase manager digital dual edge modulator digital dual edge modulator vinsen tmon0 tmon1 vccs vcc ldo blackbox vse n1 rgnd1 vse n0 rgnd0 cs3 csrtn3 cs2 csrtn2 cs1 csrtn1 cs0 csrtn0 scl sda salrt pg0 pg1 twarn en0 en1 pwm0 pwm1 pwm2 pwm3 config sa
ISL68144 fn8888 rev. 3.00 page 6 of 48 feb 8, 2018 typical application: 3+1 config uration with isl99227 sps figure 2. typical application: 3+1 configuration with isl99227 sps vcc vccs 4.7f tmon0 rgnd0 vsen 0 salrt sda scl 4.7f pwm refin tmon fault# imon pvcc vcc boot phase sw gnd vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm0 csrtn0 cs0 pwm1 csrtn1 cs1 pwm2 csrtn2 cs2 pwm3 csrtn3 cs3 470pf 470pf 470pf 470pf rgnd1 vsen 1 100 isl99227 c out vout0 vout1 c out isl99227 isl99227 ISL68144 pg0 en0 pg1 en1 1k 1k vinsen 10nf 10k 40.2k twarn config sa 12v 3.3v gnd gnd gnd 0.1f 0.1f 0.1f 0.1f 470pf 100 100 100 100 isl99227 tmon1 470pf
ISL68144 fn8888 rev. 3.00 page 7 of 48 feb 8, 2018 typical application: 2+2 config uration with isl99227 sps figure 3. typical application: 2+2 configuration with isl99227 sps vcc vccs 4.7f tmon0 rgnd0 vsen0 salrt sda scl 4.7f pwm refin tmon fault# imon pvcc vcc boot phase sw gnd vin 0. 1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0. 1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0. 1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0. 1f 2x22f 12v 5v pwm0 csrtn0 cs0 pwm1 csrtn1 cs1 pwm2 csrtn2 cs2 pwm3 csrtn3 cs3 470pf 470pf 470pf 470pf rgnd1 vsen1 100 isl99227 c out vout0 vout1 c out isl99227 isl99227 ISL68144 pg0 en0 pg1 en1 1k 1k vinsen 10nf 10k 40.2k twarn config sa 12v 3.3v gnd gnd gnd 0.1f 0.1f 0.1f 0. 1f 470pf 100 100 100 100 isl99227 tmon1 470pf
ISL68144 fn8888 rev. 3.00 page 8 of 48 feb 8, 2018 typical application: 2+2 conf iguration with dcr sensing figure 4. typical application: 2+2 configuration with dcr sensing vcc vccs tmon0 rgnd0 vsen 0 salrt sda scl 4.7f pwm0 csrtn0 cs0 pwm1 csrtn1 cs1 pwm2 csrtn2 cs2 pwm3 csrtn3 cs3 tmon1 rgnd1 vsen 1 ISL68144 pg0 en0 pg1 en1 1k 1k vinsen 10nf 10k 40.1k twarn config sa 12v 3.3v pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd vout1 c out vout0 c out
ISL68144 fn8888 rev. 3.00 page 9 of 48 feb 8, 2018 absolute maximum rating s thermal information vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.3v vccs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.6v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .(gnd - 0.3v) to vcc + 0.3v esd rating: human body model (tested per js-001-2014) . . . . . . . . . . . . . . . . . . 2kv charged device model (tested per js-001-2014) . . . . . . . . . . . . . . . 1kv latch-up (tested per jesd-78d; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance ( notes 4 , 5 ) ? ja (c/w) ? jc (c/w) 40 ld 5x5 tqfn package . . . . . . . . . . . . . . 30 1.2 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3v 5% ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 3.05v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high-effective thermal conductivity test board with ?direct attach? fe atures. see tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, v cc = 3.3v, unless otherwise specified. boldface limits apply across the operating temperature range -40c to +85c. parameter test conditions min ( note 7 )typ max ( note 7 )unit v cc supply current nominal supply current v cc = 3.3vdc; en1/2 = v ih , f sw = 400khz 63 ma shutdown supply current v cc = 3.3vdc; en1/2 = 0v, no switching 11.5 ma vccs ldo supply output voltage 1.20 1.25 1.30 v maximum current capability excluding internal load 50 ma power-on reset and input voltage lockout v cc rising por threshold 2.7 2.9 v v cc falling por threshold 1.0 v enable (en0 and en1) input high level 2.55 v enable (en0 and en1) input low level 0.8 enable (en0 and en1) input low to high ramp delay (ton_delay) 200 s por to initialization complete time 30 40 ms v cc rising por threshold 2.7 2.9 v output voltage characteristics ( note 6 ) output voltage adjustment range 0.25 3.05 v output voltage set-point accuracy set-point 0.8v to 3.05v -0.5 0.5 % set-point 0.25v to <0.8v -5 5 mv voltage sense amplifier open sense current only during open pin check of initialization 22 a input impedance (vsen - rgnd) 200 k maximum common-mode input v cc - 0.2 v maximum differential input (vsen - rgnd) 3.05 v
ISL68144 fn8888 rev. 3.00 page 10 of 48 feb 8, 2018 current sense and overcurrent protection maximum common-mode input (sps mode) csrtnx - gnd 1.6 v maximum common-mode input (dcr mode) csrtnx - gnd 3.3 v current sense accuracy isen to adc accuracy -2 2 % average overcurrent threshold resolution 0.1 a digital droop droop resolution 0.01 mv/a oscillators accuracy of switching frequency setting when set to 500khz 480 500 520 khz accuracy of switching frequency setting -4 +4 % switching frequency range 200 1000 khz soft-start rate and voltage transition rate minimum soft-start ramp rate programmable minimum rate 20 s maximum soft-start ramp rate programmable maximum rate 10 ms soft-start ramp rate accuracy -4 4 % minimum transition rate programmable minimum rate 0.1 mv/s maximum transition rate programmable maximum rate 100 mv/s transition rate accuracy -4 4 % pwm output pwmx output high level i out = 4ma v cc - 0.4 v pwmx output low level i out = 4ma 0.4 v pwmx output tri-state i ol v oh = v cc 1 a pwmx output tri-state i oh v ol = 0v -1 a thermal monitoring and protection temperature sensor range -50 150 c temperature sensor accuracy tmon to adc accuracy -4.5 4.5 % twarn output low impedance 49 13 twarn hysteresis 3c power-good and protection monitors pg output low voltage i out = 8ma load 0.4 v pg leakage current with pull-up resistor externally connected to vcc 0.5 1 a overvoltage protection threshold resolution 1mv undervoltage protection threshold resolution 1mv overvoltage protection threshold when disabled v cc - 0.2 v input voltage sense input voltage accuracy vinsen to adc accuracy -2.5 2.5 % input voltage protection threshold resolution 1mv electrical specifications recommended operating conditions, v cc = 3.3v, unless otherwise specified. boldface limits apply across the operating temperature range -40c to +85c. (continued) parameter test conditions min ( note 7 )typ max ( note 7 )unit
ISL68144 fn8888 rev. 3.00 page 11 of 48 feb 8, 2018 smbus/pmbus salert, sda output low level i out = 4ma 0.4 v scl, sda input high level 1.55 v scl, sda input low level 0.8 scl, sda input hysteresis 2mv scl frequency range 0.05 2mhz notes: 6. these parts are designed and adjusted for accuracy with all errors in the voltage loop included. 7. compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. electrical specifications recommended operating conditions, v cc = 3.3v, unless otherwise specified. boldface limits apply across the operating temperature range -40c to +85c. (continued) parameter test conditions min ( note 7 )typ max ( note 7 )unit typical performance curves figure 5. nominal supply current vs temperature figure 6. shutdown supply current vs temperature 0.03 0.04 0.05 0.06 0.07 0.08 -40-200 20406080100 ambient temperature ( o c) i cc (a) 0 0.01 0.02 0.03 0.04 0.05 -40-20 0 20406080100 ambient temperature ( o c) i cc (a)
ISL68144 fn8888 rev. 3.00 page 12 of 48 feb 8, 2018 functional description overview the ISL68144 is a digital dual ou tput, 4-phase pwm controller that can be programmed for a single ou tput 4+0, dual output 3+1, or 2+2 phase operation. operation using less than four phases between two outputs is also supported. existing digital multiphase solutions use analog comparator-based schemes (nonlinear) to bolster the inadeq uate transient response common to many digital multiphase solutions. the ISL68144 uses a linear voltage regulation scheme to address transient loads. as a result, it is much easier for users to configure and validate their designs when compared with nonlinea r schemes. by combining a proprietary low noise and zero latency digital current sense scheme with cutting edge digital design techniques, renesas is able to meet transient demands without resorting to nonlinear schemes. in addition, the isl681 44 can store up to eight user configurations in nvm and allows the user to select the desired configuration through pin-strap (config). the result is a system that is easy to configure and deploy. a number of performance enhancing features are supported in the ISL68144. these include diode braking, automatic phase dropping, dcr/resistor/smart power stage current sense support, load line regulation, and multiple temperature sensing options. to facilitate configuration development, powernavigator provides a step-by-step arrangement for setup and parametric adjustment. after a configuratio n has been set, the user can employ powernavigator to monitor telemetry or use a direct pmbus interface based on the supported command set. pwm modulation scheme the ISL68144 uses the proprietary renesas linear synthetic current modulation scheme to improve transient performance. this is a unique, constant frequency, dual-edge pwm modulation scheme with both pwm leading and trailing edges being independently moved to give th e best response to transient loads. current balance is an inherent part of the regulation scheme. the modulation scheme is capable of overlapping pulses if the load profile demand s such operation. in addition, the modulator is capable of adding or removing pulses from a given cycle in response to re gulation demands while still managing maximum average frequency to safe levels. for dc load conditions, the operat ing frequency is constant. pmbus address selection when communicating with multiple pmbus devices on a single bus, each device must have its own unique address so the host can distinguish among the devices. the device address can be set using a 1% resistor on the sa pin according to the pin-strap options listed in table 2 . phase configuration the ISL68144 supports up to two regulated outputs through seven configurable phases. either output is capable of controlling up to seven phases in any arbi trary mix. phase assignments are accomplished using powernavigator. although the device supports arbitrary phase assignment, it is good practice to assign phases to output 1 in descending sequential numerical order starting from phase 3. for example, a 3-phase rail could consist of phases 3, 2, and 1. for output 0, phases should be assigned star ting from phase 0 in ascending sequential numerical order. automatic phase add and drop to produce the most optimal efficiency across a wide range of output loading, the modulator su pports automatic dropping or adding of phases. use of automati c phase dropping is optional. if automatic phase dropping is en abled, the number of active phases at any time is determined solely by load current. during operation, phases of output 1 w ill drop beginning with the lowest phase number assigned. phase dropping begins with the highest assigned phase number. figure 7 illustrates the typical characteristic of efficiency vs load current vs phase count. phases are dropped one at a time with a user-programmed drop delay between drop events. as an example, suppose the delay is set to 1ms and three phases are active. if the load suddenly drops to a level needing only one phase, the ISL68144 will begin by dropping a phase after 1ms. an additional phase will be dropped each 1ms thereafter until only one phase remains. table 2. resistor values to address mapping r sa ( ) pmbus address r sa ( ) pmbus address 0 60h 1500 52h 180 63h 1800 53h 330 66h 2200 56h 470 67h 2700 57h 680 42h 3300 5ah 820 43h 3900 5bh 1000 46h 4700 5eh 1200 47h 5600 5fh table 2. resistor values to address mapping (continued) r sa ( ) pmbus address r sa ( ) pmbus address load (a) figure 7. efficiency vs phase number efficiency (%) i1 i2 i3 0 10 30 40 50 60 70 80 90 20
ISL68144 fn8888 rev. 3.00 page 13 of 48 feb 8, 2018 in addition to the described load current add/drop thresholds, the fast phase add function provides a very rapid response to transient load conditions. this fe ature continuously monitors the system regulation error and if it exceeds the user set threshold, all dropped phases will be readied for use. in this way, there is no delay if all phases are needed to support a load transient. the fast phase add threshold is set in powernavigator. the output current threshold for adding and dropping phases can also be configured. to ensure dropped phases have sufficient boot capacitor charge to turn on the high-side mosfet after a long disable period, a boot refresh circuit turns on the low-side mosfet of each dropped phase to refresh the boot capacitor. the frequency of the boot refresh is programmable using powernavigator. output voltage configuration output voltage set points and thresholds for each output can be configured using powernavigator. parameters such as output voltage, v out margin high/low and v out ov/uv fault thresholds can be configured with gui. ad ditionally, output voltage and margin high/low can be adjusted during regulati on through the pmbus commands vout_command, vout_margin_high, and vout_margin_low for further tuning. the following v out relationships must be mainta ined for correct operation: vout_ov_fault_limit > vout_command (vout_margin_high and vout_margin_low, if used) > vout_uv_fault_limit. additionally, the v out commands are bounded by vout_max and vout_min to provide protection against incorrect set points being sent to the device. switching frequency the switching frequency is user -configurable over a range of 200khz to 1mhz. current sensing the ISL68144 supports dcr, resistor, and smart power stage current sensing. connection to the various sense elements is accomplished through the cs and csrtn pins. current sensing inputs are high impedance differential inputs to reject noise and ground related inaccuracies. to accommodate a wide range of effective sense resistance, information about the effective sense resistance and required, per-phase current capability is used by powernavigator to properly configure the current sense circuitry. inductor dcr sensing dcr sensing takes advantage of the fact that an inductor winding has a resistive component (dcr) that will drop a voltage proportional to the inductor current. figure 8 shows that the dcr is treated as a lumped element with one terminal inaccessible for measurement. fortunately, a simple r-c network as shown in figure 9 is capable of reproducing the hidden dcr voltage. by simply matching the r-c time constant to the l/dcr time constant, it is possible to precis ely recreate the dcr voltage across the capacitor. this means that v dcr (t) = v c (t), thus preserving even the high frequency characteristic of the dcr voltage. modern inductors often have such low dcr values that the resulting signal is <10mv. to av oid noise problems, care must be taken in the pcb layout to proper ly place the r-c components and route the differential lines between controller and inductor. figure 8 shows one pcb design method that places the r component near the inductor v phase and the c component very close to the ic pins. this mi nimizes routing of the noisy v phase and maximizes filtering near the ic . the lines between the inductor and ic should be routed as a pair on a single layer directly to the controller. care must be taken to avoid routing the pair near any switching signals such as phase or pwm. this is the method used by renesas on evaluation board designs. this method senses the resistance of a metal winding in which the dcr value increases with temperature. this must be compensated or the se nsed (and reported) current will increase with temperature. to compensate for the temperature effect, the ISL68144 provides temperature sensing options and an internal methodology to apply the correction. resistive sensing for more accurate current sensing, a dedicated current sense resistor, r sense , in series with each output inductor can serve as the current sense element. however, this technique reduces the overall converter efficiency due to the additional power loss on the current sense element, r sense . a current sensing resistor has a distributed parasitic inductance, known as equivalent series induct ance (esl), typically less than 4nh. consider the esl as a separate lumped quantity, as shown in figure 9 . the phase current i l , flowing through the inductor, will also pass through the esl. similar to dcr sensing described previously, a simple r-c network across the current sense figure 8. dcr sensing configuration figure 9. sense resistor in series with inductor csn csrtnn c r dcr l ? ? l dcr r c v out v phase ic current sense csn csrtnn c r rsense esl ? ? r sense r c v out v phase ic esl current sense
ISL68144 fn8888 rev. 3.00 page 14 of 48 feb 8, 2018 resistor extracts the r sense voltage. simply match the esl/r sense time constant to the r-c time constant. figure 10 shows the sensed waveforms with and without matching rc when using resistive sense. th e pcb layout should be treated similarly to that described for dcr sense. l/dcr or esl/r sen matching assuming the compensator design is correct, figure 11 shows the expected load transient response waveforms if l/dcr or esl/r sen is matching the r-c time constant. when the load current i out has a square change, the output voltage v out also has a square response, except for the potential overshoot at load release. however, there is always some uncertainty in the true parameter values involved in th e time constant matching and therefore fine-tuning is generally required. if the r-c time constant is too large or too small, v c (t) will not accurately represent real-time i out (t) and will worsen the transient response. figure 12 shows the load transient response when the r-c timing constant is too small. in this condition, v out will sag excessively upon load insertion and might create a system failure or early overcurrent trip. figure 13 shows the transient response when the r-c time constant is too large. v out is sluggish in drooping to its final value. use these general guides if fine-tuning is needed. sps current sensing sps current sense is accomplished by sensing each sps imon output individually using vccs as a common reference. connect all sps iref input pins and all ISL68144 csrtnx input pins together and tie them to vccs, then connect the sps imonx output pins to the corresponding ISL68144 csx input pins. the signals should be run as differen tial pairs from the sps back to the ISL68144. temperature sensing the ISL68144 supports temperature sensing through bjt or smart power stage sense elements. support for bjt sense elements uses the well known delta vbe method and allows up to two sensors (mmbt3906 or similar) on each temperature sense input, tmon0 and tmon1. support for smart power stage uses a linear conversion algorith m and allows one sensor reading per pin. the conversion from voltage to temperature for smart power stage sensing is user-programmable using powernavigator. the sps temperature sensing measures the temperature dependent voltage output on the sps tmon pin. all of the sps devices attached to the output 0 rail have their tmon pins connected to the ISL68144 tmon0 pin. all of the sps devices attached to the output 1 rail have their tmon pins connected to the ISL68144 tmon1 pin. the reported temperature is that of the highest temperature sps of the group. in addition to the external temperature sense, the ic senses its own die temperature, which can be monitored using powernavigator. sensed temperature is used in the system for faults, telemetry, and temperature compensation of sensed current. temperature compensation the ISL68144 supports inductor dcr sensing, which generally requires temperature compensation due to the copper wire used to form inductors. copper has a positive temperature coefficient of approximately 0.39%/c. because the voltage across the inductor is sensed for the output current information, the sensed current has the same positive temperature coefficient as the inductor dcr. compensating current sense for temperature variation generally requires that the current-sensing element temperature and its temperature coefficient be known. although the temperature coefficient is generally obtained easily, actual current sense element temperature is nearly impossible to measure directly. instead, a temperature sensor (a bjt for the ISL68144) placed near the inductors is measured and the current sense element (dcr) temperature is calculat ed from that measurement. calculating current sense element temperature is equivalent to applying gain and offset correc tions to the temperature sensor measurement. the ISL68144 su pports both corrections. figure 14 depicts the block diagram of temperature compensation. a bjt placed near the inductors used for dcr sensing is monitored by the ic using the well known delta vbe method of temperature sensing. t sense is the direct measured temperature of the bjt. because the bjt is not directly sensing the dcr, corrections must be made so that t dcr reflects the true figure 10. voltage across r with and without rc figure 11. desired load tr ansient response waveforms figure 12. load transient response when r-c time constant is too small figure 13. load transient response when r-c time constant is too large mismatched rc matched rc i out v out i out v out i out v out
ISL68144 fn8888 rev. 3.00 page 15 of 48 feb 8, 2018 dcr temperature. corrections are applied according to the relationship shown in equation 1 , where k slope represents a gain scaling and t offset represents an offset correction. the designer can use powernavigator to provide the parameters: after t dcr has been determined, the compensated dcr value can be determined according to equation 2 , where dcr 25 is the dcr at +25c and t c is the temperature coefficient of copper (3900 ppm/c). t dcr = t actual here: thus, the temperature compensated dcr is now used to determine the actual value of current in the dcr sense element. in the physical pcb design, the temperature sense diode (bjt) is placed close to the inductor of the phase that is never dropped during automatic phase drop oper ation. additionally, a filter capacitor no larger than 500pf should be added near the ic between each tempx pin and vccs as shown in figure 15 . lossless input current and power sensing input current telemetry is prov ided through an input current synthesizer. by using the ic?s ability to precisely determine its operational conditions, input current can be synthesized to a high degree of accuracy without the need for a lossy sense resistor. fine-tuning of offset and gain are provided for in the gui. note that input current sense fine-tuning must be done after output current sense setup is finalized. with a precise knowledge of input current and voltage, input power can be computed. input current and power telemetry is accessed through pmbus and easily monitored in powernavigator. voltage regulation output voltage is sensed through the remote sense differential amplifier and digitized. from this point, the regulation loop is entirely digital. traditional pid controls are used in conjunction with several enhanced methods to compensate the voltage regulation loop and tune the transient response. current feedback current feedback in a voltage regulator is often used to ease the stability design of the voltage feedback path. additionally, many microprocessors require the voltage regulator to have a controlled output resistance (k nown as load line or droop regulation) and this is accomp lished using current feedback. for applications requiring droop regulation, the designer simply specifies the output resistance desired using powernavigator. current feedback stability benefits are available for rails that do not specify droop regulation such as system agent. for these applications, the designer can enable the ac current feedback in the gui. with this configuration, the dc output voltage will be steady regardless of load current. t dcr k slope t sense t offset + ? = (eq. 1) dcr corr dcr 25 1t c + t actual 25 C ?? ? ?? ? = (eq. 2) figure 14. block diagram of temperature compensation vbe vccs tmonx t offset t sense v out dcr current sense iphase# t c temperature compensation dcr corr to telemetry csx csrtnx k slope ic iphase# sw1 sw2 sw3 output 1 l2 l3 l1 sw0 output 0 tmon1 vccs ic tmon0 l0 optional auxiliary temperature sense optional auxiliary temperature sense figure 15. recommended placement of temperature sensors figure 16. input voltage sense configuration adc vinsen ic 40.2k v in 10k 10nf
ISL68144 fn8888 rev. 3.00 page 16 of 48 feb 8, 2018 power-on reset (por) initialization of the ISL68144 begins after v cc crosses its rising por threshold. when por conditions are met, the internal 1.2v ldo is enabled and basic digital subsystem integrity checks begin. during this process, the co ntroller will load the selected user configuration from nvm as indicated by the config pin resistor value, read v in uvlo thresholds from memory, and start the telemetry subsystem. with telemetry enabled, v in can be monitored to determine when it exceeds its user-programmable, rising uvlo threshold. after v cc and v in satisfy their respective voltage conditions, the co ntroller is in its shutdown state. it will transition to its active state and begin soft-start when the state of the en0/en1 command is at start-up. while in shutdown mode, the pwm outputs are held in a hi gh-impedance state to ensure the drivers remain off. soft-start delay and ramp times it might be necessary to set a de lay from when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer might want to precisely set the time required for an output to ramp to its target value after the delay period has expired. these features can be used as part of an overall inrush current manage ment strategy or to precisely control how fast a load ic is tu rned on. the ISL68144 gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start delay and ramp-up/down times can be configured using powernavigator. the device needs approximately 200s after enable to initialize before starting to ramp up. when the soft-start ramp period is set to 0m s, the output ramps up as quickly as the output load capacitance and loop settings allow. it is recommended to set the ramps to a non-zero value to prevent inadvertent fault conditions du e to excessive inrush current. stored configuration selection as many as eight configurations can be stored and used at any time using the on-board nonvolat ile memory. configurations are assigned an identifier number between 0 and 7 at power-up. the device loads the configuration indicated by the 1% resistor value detected on the config pin. resistor values are used to indicate one of the eight possible configurations. table 3 provides the resistor value corresponding to each configuration identifier. only the most recent configuration with a given number can be loaded. the device supports a total of eight stored operations. as an example, a configuration with the identifier 0 could be saved eight times or configurations with all eight identifiers could be stored one time each for a total of eight save operations. powernavigator provides a simple interface to save and load configurations. fault monitoring and protection the ISL68144 actively monitors te mperature, input voltage, output voltage, and output current to detect and report fault conditions. fault monitors trigger configurable protective measures to prevent damage to a load. the power-good indicators, pg0/pg1, are provided for linking to external system monitors. a high level of flexibility is provided in the ISL68144 fault logic. faults can be enabled or disabled individually. each fault type can also be configured to either latch off or retry indefinitely. power-good signals the pg0/pg1 pins are open-drain, power-good outputs that indicate completion of the so ft-start sequence and output voltage of the associated rail within the expected regulation range. the pg pins can be associated or disassociated with a number of the available fault types. this allows a system design to be tailored for almost any condition. in addition, these power-good indicators will be pulled low when a fault (ocp or ovp) condition or uv condition is detected on the associated rail. output voltage protection output voltage is measured at the load sensing points differentially for regulation and the same measurement is used for ovp and uvp. the fault thresholds are set using pmbus commands. figure 17 on page 17 shows a simplified ovp/uvp block diagram. the output voltag e comparisons are done in the digital domain. the device responds to an output overvoltage condition by disabling the output, declaring a fault, setting the salrt pin, setting the pg pin, and then pulsing the lfet until the output voltage has dropped below the threshold. similarly, the device responds to an output undervoltage condition by disabling the output, declaring a fault, setting the salrt pin, and setting the pg pin. the output will not restart until the en pin is cycled (unless the device is configured to retry). in addition, the ISL68144 features open pin sensing protection to detect an open on the output volt age sensing circuit. this open is table 3. resistor values to configuration mapping r config ( ) config id 6800 0 1800 1 2200 2 2700 3 3300 4 3900 5 4700 6 5600 7 table 3. resistor values to configuration mapping (continued) r config ( ) config id
ISL68144 fn8888 rev. 3.00 page 17 of 48 feb 8, 2018 detected as an ovp condition, which suspends the controller operation. output current protection the ISL68144 offers a comprehensive overcurrent protection scheme. each phase is protected from both excessive peak current and sustained current. in addition, the system is protected from sustained total output overcurrent. figure 18 shows a block diagram of the system total output current protection scheme. in this scheme, the phase currents are summed to form isum. isum is then fed to dual response paths allowing the user to program separate lpf, threshold, and response time. one path is inte nded to allow response more quickly than the other path. with this system, the user can allow high peak total current for a short time and a lower level of current for a sustained time. note that neither of these paths affect pwm activity on a cycle-by -cycle basis. the characteristics of each path are easily set in powernavigator. in addition to total output curr ent, the ISL68144 provides an individual phase peak current li mit that will act on pwm in a cycle-by-cycle manner. this means that if a phase current is detected to exceed the oc threshold, the phase pwm signal will be inverted to move current away from the threshold. in addition to limiting positive or negative peak current on a cycle-by-cycle basis, individual phase oc can be configured to limit current indefinitely or to declare a faul t after a programmable number of consecutive oc cycles. this feat ure is useful for applications where a fault shutdown of the sy stem would not be acceptable but some ability to limit phase currents is desired. figures 21 and 22 show this operation. if configured for indefinite current limit, the converter will act as a current source and v out will not remain at its regulation point. it should be noted that in this case, v out ov or uv protection action might occur, which could shut the regulator down. examples of ocp_fast and ocp_slow waveforms are shown in figures 19 and 20 . figure 17. ovp, uvp comparators rgndx vsenx adc ic digital ov comparator threshold register + - digital uv comparator threshold register + - soc ph1 current synthesizer isum phn current synthesizer timer to fault block filter compare timer act filter fast sum oc limit delay timer to fault block filter compare timer act filter slow sum oc limit delay total output current fault switching period count to fault block compare count act +peak limit occount f sw clk -peak limit pulse by pulse limit may be set for indefinite limiting but no fault assertion switching period count to fault block compare count act uccount f sw clk pulse by pulse limit phase peak current limiting and fault iphasen negative peak limiting positive peak limiting may be set for indefinite limiting but no fault assertion ?? pgood pwm ocp_slow_threshold ocp_fast_threshold ocp_fast counter filter time constant pgood pwm ocp_fast_threshold ocp_slow_threshold ocp_slow counter filter time constant
ISL68144 fn8888 rev. 3.00 page 18 of 48 feb 8, 2018 smart power stage oc fault detect renesas smart power stage (sps) devices will output a large signal on their imon lines if peak current exceeds their preprogrammed threshold. (for more detail about this functionality, refer to the relevant sps datasheet.) the ISL68144 is equipped to detect this fault flag and immediately shut down. this detector is enabled on the powernavigator overcurrent fault setup screen. this feature functions by dete cting signals that exceed the current sense adc full scale range. if this detector is disabled while using a renesas sps, the sps fault# signal must be connected to the controller enable pin of the associated rail. this will ensure that an sps oc event will be detected and the converter will shut down. thermal monitoring (twarn) and protection the twarn pin indicates the temperature status of the voltage regulator. the twarn pin is an open-drain output and an external pull-up resistor is required. this signal is valid only after the controller is enabled. the twarn signal can be used to inform the system that the temperature of the voltage regulator is too high and the load should reduce its power consum ption. twarn indicates only thermal warnings, not faults. the thermal monitoring function block diagram is shown in figure 23 . the ISL68144 has two over-temperature thresholds, which allow both warning and fault indications. each temperature sensor threshold can be independently programmed in the powernavigator gui. figure 24 shows the thermal warning to twarn and figure 25 shows the over-temperature fault to shutdown. pgood and twarn can be configured in powernavigator to indicate these warning and fault thresholds. figure 21. positive peak phase current limiting figure 22. negative peak phase current limiting twarn pgood pwm positive_current_limiting_per_phase twarn pgood pwm negative_current_limiting_per_phase twarn vccs telemetry control tmax temp sensors temp monitor adc ic tmonx delta vbe low ot threshold high ot threshold pwm pgood twarn pwm pgood twarn high ot threshold low ot threshold
ISL68144 fn8888 rev. 3.00 page 19 of 48 feb 8, 2018 layout and design considerations in addition to tb379 , the following pcb layout and design strategies are intended to minimize noise coupling and the impact of board parasitic impedances on converter performance. in addition, these strategies optimize the heat dissipating capabilities of the printed circuit board. this section highlights some important practices, which should be followed during the layout process. table 4 provides general guidance on best practices related to pin noise sensitivity. good engine ering judgment is required to implement designs based on criter ia specific to the situation. table 4. pin design and/or layout considerations pin name noise sensitive description vinsen yes connects to the resistor divider between vin and gnd (see figure 16 on page 15 ). filter vinsen with 10nf to gnd. rgndx vsenx yes treat each of the remote voltage sense pairs as differential signals in the pcb layout. they should be routed side by side on the same layer. they should not be routed in proximity to noisy signals like pwm or phase. tie to ground when not used. pgx no open-drain. 3.3v maximum pull-up voltage. tie to ground when not used. scl, sda, salrt yes signals between 50khz to 2mhz during communication should be paired up with salrt and routed carefully. use 20 mils spacing within sda, salrt, and scl, and more than 30 mils to all other signals. refer to the smbus design guidelines and place proper termination resistance for impedance matching. tie to ground when not used. tmonx yes when diode sensing is used, vccs is the return path for the delta vbe currents. use a separate vccs route specifically for diode temp sense. a filter capacitor no greater than 500pf should be placed between each temp pin and the vccs pin near the ic. tie to ground when not used. twarn no open-drain. 3.3v maximum pull-up voltage. vcc yes place at least a 2.2f mlcc decoupling capacitor directly at the pin. vccs yes place a 4.7f mlcc decoupling capacitor directly at the pin. pwmx no avoid routing near noise sensitive analog lines such as current sense or voltage sense. csx csrtnx yes treat each of the current sense pairs as differential signals in the pcb layout. they should be routed side by side on the same layer. they should not be routed in proximity to noisy signals like pwm or phase. proper routing of current sense is perhaps the most critical of all the layout tasks. tie to ground when not used. gnd yes this epad is the return of pwm output drivers. use four or more vias to directly connect the epad to the power ground plane. general comments the layer next to the top or bottom layer is preferred to be ground layers, although the signal layers can be sandwiched in the ground layers if possible. table 4. pin design and/or layout considerations (continued) pin name noise sensitive description
ISL68144 fn8888 rev. 3.00 page 20 of 48 feb 8, 2018 pmbus operation the ISL68144 pmbus slave address is pin selectable, using the address pin and resistor value described in table 2 on page 12 . for proper operation, users should follow the pmbus protocol, as shown in ? pmbus protocol ? on page 21 . the supported pmbus addresses are in 8-bit format (inc luding write and read bit), see table 5 . the least significant bit of the 8-bit address is for write (0h) and read (1h). pmbus comm ands are in the range from 0x00h to 0xffh. for the ISL68144, page 0 corresponds to output 0 and page 1 to output 1. for reference purposes, the 7-bit format addresses are also summarized in table 5 . the pmbus data formats follow pmbus specification version 1.3 and smbus version 2.0. basic pmbus telemetry comm ands are summarized in ? pmbus command summary ? on page 22 . table 5. pmbus 8-bit and 7-bit format address (hex) 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 80/81 40 a0/a1 50 b0/b1 58 c0/c1 60 82/83 41 a2/a3 51 b2/b3 59 c2/c3 61 84/85 42 a4/a5 52 b4/b5 5a c4/c5 62 86/87 43 a6/a7 53 b6/b7 5b c6/c7 63 88/89 44 a8/a9 54 b8/b9 5c c8/c9 64 8a/8b 45 aa/ab 55 ba/bb 5d ca/cb 65 8c/8d 46 ac/ad 56 bc/bd 5e cc/cd 66 8e/8f 47 ae/af 57 be/bf 5f ce/cf 67 figure 26. simplified pmbus initialization timing diagram 1.2v vcc enable ~30ms vccs indefinitely pmbus command pmbus command pmbus command pmbus command v out program configuration (bt, tmax, ps, de, etc.) program configuration (bt, tmax, ps, de, etc.) use previous programmed configuration for star-up and operation vccs 3.3v por pll locked fac load config tel adc initialized start-up diagnostics done done customer config load program configuration (bt, tmax, ps, de, etc.)
ISL68144 fn8888 rev. 3.00 page 21 of 48 feb 8, 2018 pmbus protocol s slave address_0 1 7 + 1 command code 1 8 low data byte high data byte pec a 1 8 a 1 8 a 1 8 a 1 a 1 p s slave address_0 7 + 1 command code 1 8 a 1 a pec 8 1 a 1 p optional 9 bits for smbus/pmbus 1. send byte protocol 2. write byte/word protocol s slave address_0 1 7 + 1 command code 1 8 a 1 8 a 1 8 a 1 8 a 1 n 1 p 3. read byte/word protocol rs slave address_1 1 7 + 1 example command: 03h clear faults example command: 21h vout_command not used in i 2 c optional 9 bits for smbus/pmbus not used in i 2 c optional 9 bits for smbus/pmbus not used in i 2 c example command: 8b re ad_vout (two words, read voltage of the s elected rail). s: start condition a: acknowledge (0) n: not acknowledge (1) rs: repeated start condition p: stop condition pec: packet error checking r: read (1) w: write (0) 5. alert response address (ara, 0001_1001, 25h) for smbus and p mbus, not used for i 2 c s alert addr_1 1 7 + 1 1 7+1 a 1 a 8 1 a 1 p optional 9 bits for smbus/pmbus not used in i 2 c 1 a data byte pec 8 1 8 1 a 4. group command protocol - no more than one command can be sen t to the same address s slave addr2_0 1 7 + 1 1 a s slave addr1_0 1 7 + 1 command code 1 8 low data byte high data byte pec a 1 8 a 1 8 a 1 8 a 1 a low data byte high data byte pec 8 1 8 a 1 8 a 1 a 1 p rs slave addr3_0 1 7 + 1 optional 9 bits for smbus/pmbus 1 a not used in i 2 c not used for one byte word read not used for one byte word slave_address_1 pec low data byte high data byte pec command code 8 1 a command code 8 a (this will clear all of the bits in status byte for the selecte d rail) acknowledge or data from slave, ISL68144 controller stop (p) bit is not allowed before the repeated start condition when reading contents of a register. a
ISL68144 fn8888 rev. 3.00 page 22 of 48 feb 8, 2018 pmbus command summary code command name description type data format default value default setting 00h page selects output 0, 1, or both r/w bit 00h page 0 01h operation enable/disable, margin settings r/w bit 08h off 02h on_off_config on/off configuration settings r/w bit 16h enable pin control 03h clear_faults clears all fault bits in all registers and releases the salrt pin write n/a n/a 10h write_protect write protection to sets of commands r/w bit 00h no write protection 20h vout_mode defines format for output voltage related commands read bit 40h direct format 21h vout_command sets the nominal v out target r/w direct 0384h 900mv 22h vout_trim applies trim voltage to v out set-point r/w direct 0000h 0mv 24h vout_max absolute maximum voltage setting r/w direct 08fch 2300mv 25h vout_margin_high sets v out target during margin high r/w direct 0640h 1600mv 26h vout_margin_low sets v out target during margin low r/w direct 00fah 250mv 27h vout_transition_rate slew rate setting for v out changes r/w direct 0064h 10mv/s 28h vout_droop sets the load line (v/i slope) resistance for the output r/w direct 0000h 0v/a 2bh vout_min absolute minimum target voltage setting r/w direct 0000h 0v 40h vout_ov_fault_limit sets the v out overvoltage fault threshold r/w direct 076ch 1900mv 44h vout_uv_fault_limit sets the v out undervoltage fault threshold r/w direct 0000h 0mv 4fh ot_fault_limit sets the over-temperature fault threshold r/w direct 007dh +125c 51h ot_warn_limit sets the over-temperature warn threshold r/w direct 07d0h +2000c 55h vin_ov_fault_limit sets the v in overvoltage fault threshold r/w direct 36b0h 14,000mv 59h vin_uv_fault_limit sets the v in undervoltage fault threshold r/w direct 1f40h 8,000mv 5bh iin_oc_fault_limit sets the i in overcurrent fault threshold r/w direct 0032h 50a 60h ton_delay sets the delay time from enable to v out rise r/w direct 0014h 200s 61h ton_rise turn-on rise time r/w direct 01f4h 500s 64h toff_delay turn-off delay time r/w direct 0000h 0s 65h toff_fall turn-off fall time r/w direct 01f4h 500s 78h status_byte first byte of status_word read bit n/a n/a 79h status_word summary of critical faults read bit n/a n/a 7ah status_vout reports v out faults read bit n/a n/a 7bh status_iout reports i out faults read bit n/a n/a 7ch status_input reports input faults read bit n/a n/a 7dh status_temperature reports temperature warnings/faults read bit n/a n/a 7eh status_cml reports communication, memory, logic errors read bit n/a n/a 80h status_mfr_specific reports specific events read bit n/a n/a 88h read_vin reports input voltage measurement read direct n/a n/a 89h read_iin reports input current measurement read direct n/a n/a 8bh read_vout reports output voltage measurement read direct n/a n/a 8ch read_iout reports output current measurement read direct n/a n/a
ISL68144 fn8888 rev. 3.00 page 23 of 48 feb 8, 2018 pmbus use guidelines all commands can be read at any time. always disable the outputs when writing comma nds that change device settings. exceptions to this rule are commands intended to be written while the device is enabled, for example, operation. pmbus data formats direct (d) the direct data format is a 2-byte two?s complement binary integer. bit field (bit) a breakdown of the bit field format is provided in ? pmbus command detail ? on page 24 . 8dh read_temperature_1 reports internal temperature measurement read direct n/a n/a 8eh read_temperature_2 reports tmon0 te mperature measurement read direct n/a n/a 8fh read_temperature_3 reports tmon1 te mperature measurement read direct n/a n/a 96h read_pout reports output power read direct n/a n/a 97h read_pin reports input power read direct n/a n/a 98h pmbus_revision reports specific events read bit 33h revision 1.3 adh ic_device_id reports device identification information block read bit 49d22200h ISL68144 aeh ic_device_rev reports device revision information block read bit n/a n/a e7h apply_settings instructs device to apply pmbus setting changes write bit 01h n/a f2h restore_config allows selection of configurations from nvm write bit n/a n/a pmbus command summary (continued) code command name description type data format default value default setting
ISL68144 fn8888 rev. 3.00 page 24 of 48 feb 8, 2018 pmbus command detail page (00h) definition: selects controller 0, controller 1, or bo th controllers 0 and 1 to receive comman ds. all commands following this command will be received and acted on by th e selected controller or controllers. data length in bytes: 1 data format: bit field type: r/w default value: 00h units: n/a operation (01h) definition: sets the enable state when configured for pmbus enable. sets output voltage margin settings. the device always acts on faults during margin. the following table reflects the valid settings for the device. paged or global: paged data length in bytes : 1 data forma t: bit field type : r/w default value : 08h command page (00h) format bit field bit position76543210 access r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value00000000 bits 7:4 bits 3:0 page 0000 0000 0 0000 0001 1 1111 1111 both command operation (01h) format bit field bit position76543210 access r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value00001000 bit number purpose bit value meaning bits 7:6 enable/disable 00 immediate off (decay) 01 soft-off (use toff_delay and toff_fall) 10 on bits 5:4 v out source 00 vout_command 01 vout_margin_low 10 vout_margin_high 11 not used bits 3:2 margin response 10 act on faults bit 1:0 not used 0 not used
ISL68144 fn8888 rev. 3.00 page 25 of 48 feb 8, 2018 on_off_config (02h) definition: configures the interpretation of the op eration command and the enable pin (en). paged or global: global data length in bytes: 1 data format: bit field type: r/w default value: 16h (enable pin control) clear_faults (03h) definition: clears all fault bits in all registers and releases the salrt pin (if asserted) simultaneously. if a fault condition still exit s, the bit will reassert immediately. this command will not restart a device if it is shut down, it will only clear the faults. paged or global: global data length in bytes: 0 data format: n/a type: write only default value: n/a units: n/a command on_off_config (02h) format bit field bit position76543210 access r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value00000000 bit number purpose bit value meaning 7:5 not used 000 not used 4:2 sets the source of enable 000 device always enabled regardless of pin or operation command state 101 device starts from enable pin only 110 device starts from operation command only 111 device starts from operation command and enable pin 1 enable pin polarity 1 active high only 0 enable pin turn-off action 1 turn off immediately with decay 0 use programmed toff_delay and toff_fall settings
ISL68144 fn8888 rev. 3.00 page 26 of 48 feb 8, 2018 write_protect (10h) definition: sets the write protection of certain configuration commands. paged or global: global data length in bytes: 1 data format: bit field type: r/w default value: 00h (enable all writes) units: n/a vout_mode (20h) definition: returns the supported v out mode. this device supports only absolute direct mode. paged or global: global data length in bytes: 1 data format: bit field type: read only default value: 40h units: n/a equation: n/a range : n/a vout_command (21h) definition: sets the value of v out when the operation command is configured for nominal operation. paged or global: paged data length in bytes: 2 data format: direct type: r/w default value: 0384h (900mv) units: mv equation: vout_command = (direct value) range : vout_min to vout_max command write_protect (10h) format bit field bit position76543:0210 access r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value00000000 settings protection 40h disables all writes except to write_protect, operation, clear_faults, page 20h disables all writes except al l above plus on_off_config and v out_command, vout_trim 00h enables all writes note: any settings other than the three shown in th e table will result in an invalid data fault. command vout_command (21h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000001110000100
ISL68144 fn8888 rev. 3.00 page 27 of 48 feb 8, 2018 vout_trim (22h) definition: sets a fixed trim voltage to the output voltage command value. this command is typically used to calibrate a device in the application circuit. paged or global: paged data length in bytes: 2 data format: direct type: r/w default value: 0000h (0mv) units: mv equation: vout_trim = (direct value) range : 250mv vout_max (24h) definition: sets the maximum allowed v out target regardless of any other commands or combinations. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 08fch (2300mv) units: mv equation: vout_max = (direct value) range : 0mv to 3300mv command vout_trim (22h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function two?s complement integer default value 0000000000000000 command vout_max (24h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000100011111100
ISL68144 fn8888 rev. 3.00 page 28 of 48 feb 8, 2018 vout_margin_high (25h) definition: sets the value of v out when the operation command is configured for margin high. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0640h (1600mv) units: mv equation: vout_margin_high = (direct value) range : vout_min to vout_max vout_margin_low (26h) definition: sets the value of v out when the operation command is configured for margin low. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 00fah (250mv) units: mv equation: vout_margin_low = (direct value) range : vout_min to vout_max command vout_margin_high (25h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000011001000000 command vout_margin_low (26h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000000011111010
ISL68144 fn8888 rev. 3.00 page 29 of 48 feb 8, 2018 vout_transition_rate (27h) definition: sets the output voltage rate of change during regulation. changes to this setting requir e a write to the apply_settings command before the change will take effect. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0064h (10mv/s) units: v/s equation: vout_transition_rate = (direct value)*100 range : 100v/s to 100mv/s vout_droop (28h) definition: sets the output voltage rate of change during regulation. changes to this setting require a write to the apply_settings command before the change will take effect. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0000h (0v/a) units: v/a equation: vout_droop = (direct value)*10 range : 0mv/a to 16mv/a command vout_transition_rate (27h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000000001100100 command vout_droop (28h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000000000000000
ISL68144 fn8888 rev. 3.00 page 30 of 48 feb 8, 2018 vout_min (2bh) definition: sets the minimum allowed v out target regardless of any other commands or combinations. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0000h (0mv) units: mv equation: vout_min = (direct value) range : 0v to vout_max vout_ov_fault_limit (40h) definition: sets the output overvoltage fault threshold. changes to this setting require a write to the apply_settings command before the change will take effect. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 076ch (1900mv) units: mv equation: vout_ov_fault_limit = (direct value) range : 0v to vout_max command vout_min (2bh) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000000000000000 command vout_ov_fault_limit (40h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000011101101100
ISL68144 fn8888 rev. 3.00 page 31 of 48 feb 8, 2018 vout_uv_fault_limit (44h) definition: sets the v out undervoltage fault threshold. this fault is masked during ramp or when disabled. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0000h (0mv) units: mv equation: vout_uv_fault_limit = (direct value) range : 0v to vout_max ot_fault_limit (4fh) definition: sets the power stage over -temperature fault limit. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 007dh (+125c) units: c equation: ot_fault_limit = (direct value) range : 0c to +2000c command vout_uv_fault_limit (44h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000000000000000 command ot_fault_limit (4fh) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function two?s complement integer default value 0000000001111101
ISL68144 fn8888 rev. 3.00 page 32 of 48 feb 8, 2018 ot_warn_limit (51h) definition: sets the system over-temperature warn limit. if any measured temperature exceeds this value, the device will: ? set the temperature bit in status_byte and status_word ? set the ot_warning bit in status_temperature ? set the salrt pin ?set the twarn pin paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 07d0h (+2000c) units: c equation: ot_warn_limit = (direct value) range : 0c to +2000c vin_ov_fault_limit (55h) definition: sets the v in overvoltage fault threshold. changes to this setting re quire a write to the apply_settings command before the change will take effect. paged or global: global data length in bytes: 2 data format: direct type: r/w default value: 36b0h (14,000mv) units: mv equation: vin_ov_fault_limit = (direct value) range : 0mv to 16,000mv command ot_warn_limit (51h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function two?s complement integer default value 0000011111010000 command vin_ov_fault_limit (55h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0011011010110000
ISL68144 fn8888 rev. 3.00 page 33 of 48 feb 8, 2018 vin_uv_fault_limit (59h) definition: sets the v in undervoltage fault threshold. also referred to as unde rvoltage lockout (uvlo). changes to this setting require a write to the apply_settings command before the change will take effect. paged or global: global data length in bytes: 2 data format: direct type: r/w default value: 1f40h (8,000mv) units: mv equation: vin_uv_fault_limit = (direct value) range : 0mv to 16,000mv iin_oc_fault_limit (5bh) definition: sets the i in overcurrent fault threshold. changes to this setting require a write to the apply_settings command before the change will take effect. paged or global: global data length in bytes: 2 data format: direct type: r/w default value: 0032h (50a) units: a equation: iin_oc_fault_limit = (direct value) range : 0a to 50a command vin_uv_fault_limit (59h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0001111101000000 command iin_oc_fault_limit (5bh) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000000000110010
ISL68144 fn8888 rev. 3.00 page 34 of 48 feb 8, 2018 ton_delay (60h) definition: sets the delay time of v out during enable. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0014h (200s) units: s equation: ton_delay = (direct value)*10 range : 200s to 655,340s ton_rise (61h) definition: sets the rise time of v out during enable. changes to this setting requir e a write to the apply_settings command before the change will take effect. this function uses the value of v out to calculate rise time, so apply_ settings must be sent after any change to the v out target for accurate rise time. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 01f4h (500s) units: s equation: ton_rise = (direct value) range : 0s to 10,000s command ton_delay (60h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000000000010100 command ton_rise (61h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000000111110100
ISL68144 fn8888 rev. 3.00 page 35 of 48 feb 8, 2018 toff_delay (64h) definition: sets the delay time of vout during disable. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0000h (0s) units: s equation: toff_delay = (direct value)*10 range : 0s to 100,000s toff_fall (65h) definition: sets the fall time of v out during disable. changes to this setting require a write to the apply_settings command before the change will take effect. this function uses the value of v out to calculate fall time, so apply_settings must be sent after any change to the v out target for accurate fall time. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 01f4h (500s) units: s equation: toff_fall = (direct value) range : 0s to 10,000s command toff_delay (64h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000000000000000 command toff_fall (65h) format direct bit position 1514131211109876543210 access r/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/wr/w function unsigned integer default value 0000000111110100
ISL68144 fn8888 rev. 3.00 page 36 of 48 feb 8, 2018 status_byte (78h) definition: returns a summary of the unit?s fault status. based on the info rmation in this byte, the host can get more information by reading the appropriate status registers. a fault in either output will be reported here. paged or global: global data length in bytes: 2 data format: bit field type : read only default value: n/a units: n/a command status_byte (78h) format bit field bit position76543210 access rrrrrrrr function see following table bit number status bit name meaning 7not used not used 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory, or logic fault has occurred. 0 none of the above a status change other than those listed above has occurred.
ISL68144 fn8888 rev. 3.00 page 37 of 48 feb 8, 2018 status_word (79h) definition: returns a summary of the device?s fault status. based on the in formation in these bytes, the host can get more information by reading the appropriate status registers. a fault in either output will be re ported here. the low byte of the status_word co ntains the same information as the status_byte (78h) command. paged or global: global data length in bytes: 2 data format: bit field type : read only default value: n/a units: n/a command status_word (79h) format bit field bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function see following table bit number status bit name meaning 15 v out an output voltage fault has occurred. 14 iout an output current fault has occurred. 13 input an input voltage fault has occurred. 12 mfr_specific a manufacturer specific event has occurred. 11 power_good # the power_good signal, if present, is negated. ( note 8 ) 10:7 not used not used 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory, or logic fault has occurred. 0 none of the above a status change other than those listed above has occurred. note: 8. if the power_good# bit is set, this indicates that the power_g ood signal, if present, is signal ing that the output power is n ot good.
ISL68144 fn8888 rev. 3.00 page 38 of 48 feb 8, 2018 status_vout (7ah) definition: returns a summary of output voltage faults. paged or global: paged data length in bytes: 1 data format: bit field type : read only default value: n/a units: n/a status_iout (7bh) definition: returns a summary of output current faults. paged or global: paged data length in bytes: 1 data format: bit field type : read only default value: n/a units: n/a command status_vout (7ah) format bit field bit position76543210 access rrrrrrrr function see following table bit number status bit name meaning 7 vout_ov_fault indicates an output overvoltage fault. 6:5 not used not used 4 vout_uv_fault indicates an output undervoltage fault. 3 vout_max warning indicates an output voltage maximum warning. 2:0 not used not used command status_iout (7bh) format bit field bit position76543210 access rrrrrrrr function see following table bit number meaning 7 an output overcurrent fault has occurred. 6 an output overcurrent and undervoltage fault has occurred. 5:4 not used 3 a current share fault has occurred. 2:0 not used
ISL68144 fn8888 rev. 3.00 page 39 of 48 feb 8, 2018 status_input (7ch) definition: returns a summary of input voltage faults. paged or global: global data length in bytes: 1 data format: bit field type : read only default value: n/a units: n/a status_temperature (7dh) definition: returns a summary of temperature related faults. paged or global: global data length in bytes: 1 data format: bit field type : read only default value: n/a units: n/a command status_input (7ch) format bit field bit position76543210 access rrrrrrrr function see following table bit number meaning 7 an input overvoltage fault has occurred. 6:5 not used 4 an input undervoltage fault has occurred. this fault is initially masked until v in exceeds the uv threshold. 3not used 2 an input overcurrent fault has occurred. 1:0 not used command status_temperature (7dh) format bit field bit position76543210 access rrrrrrrr function see following table bit number meaning 7 an over-temperature fault has occurred. 6 an over-temperature warning has occurred. 5not used 4 an under-temperature fault has occurred. 3:0 not used
ISL68144 fn8888 rev. 3.00 page 40 of 48 feb 8, 2018 status_cml (7eh) definition: returns a summary of any communicatio ns, logic, and/or memory errors. paged or global: global data length in bytes: 1 data format: bit field type : read only default value: n/a units: n/a status_mfr_specific (80h) definition: returns the status of specific information detailed below. paged or global: global data length in bytes: 1 data format: bit field type: read only default value: n/a units: n/a command status_cml (7eh) format bit field bit position76543210 access rrrrrrrr function see following table bit number meaning 7 invalid or unsupported pmbus command was received. 6 the pmbus command was sent with invalid or unsupported data. 5 a packet error was detected in the pmbus command. 4 memory fault detected. 3 processor fault detected. 2not used 1 a communication fault other than the on es listed in this table has occurred. 0 a memory or logic fault not listed above was detected. command status_mfr_specific (80h) format bit field bit position76543210 access rrrrrrrr function see following table bit number meaning 7:2 not used 1 otp nvm memory is full. 0not used
ISL68144 fn8888 rev. 3.00 page 41 of 48 feb 8, 2018 read_vin (88h) definition: returns the input voltage reading. paged or global: global data length in bytes: 2 data format: direct type: read only default value: n/a units: mv equation: read_vin = (direct value) read_iin (89h) definition: returns the input current reading. paged or global: global data length in bytes: 2 data format: direct type: read only default value: n/a units: a equation: read_iin = (direct value)/100 read_vout (8bh) definition: returns the output voltage reading. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: mv equation: read_vout = (direct value) command read_vin (88h) format direct bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_iin (89h) format direct bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_vout (8bh) format direct bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer
ISL68144 fn8888 rev. 3.00 page 42 of 48 feb 8, 2018 read_iout (8ch) definition: returns the output current reading. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: a equation: read_iout = (direct value)/10 read_temperature_1 (8dh) definition: returns the temperature reading of the power stage. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: ? c equation: read_temperature_1 = (direct value) read_temperature_2 (8eh) definition: returns the temperature reading from a remote diode connected to tmon0 when configured for diode sensing. paged or global: global data length in bytes: 2 data format: direct type: read only default value: n/a units: ? c equation: read_temperature_2 = (direct value) command read_iout (8ch) format direct bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_temperature_1 (8dh) format direct bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_temperature_2 (8eh) format direct bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer
ISL68144 fn8888 rev. 3.00 page 43 of 48 feb 8, 2018 read_temperature_3 (8fh) definition: returns the temperature reading from a remote diode connected to tmon1 when configured for diode sensing. paged or global: global data length in bytes: 2 data format: direct type: read only default value: n/a units: ? c equation: read_temperature_3 = (direct value) read_pout (96h) definition: returns the output power. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: w equation: read_pout = (direct value) read_pin (97h) definition: returns the input power. paged or global: global data length in bytes: 2 data format: direct type: read only default value: n/a units: w equation: read_pin = (direct value) command read_temperature_3 (8fh) format direct bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_pout (96h) format direct bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_pin (97h) format direct bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer
ISL68144 fn8888 rev. 3.00 page 44 of 48 feb 8, 2018 pmbus_revision (98h) definition: returns the revision of the pmbus specific ation to which the device is compliant. data length in bytes: 1 data format: bit field type: read only default value: 33h (part 1 revision 1.3, part 2 revision 1.3) units: n/a ic_device_id (adh) definition: returns device identification information. paged or global: global data length in bytes: 4 data format: bit field type: block read default value: 49d22200h units: n/a ic_device_rev (aeh) definition: returns device revision information. paged or global: global data length in bytes: 4 data format: bit field type: block read default value: n/a units: n/a command pmbus_revision (98h) format bit field bit position76543210 access rrrrrrrr function see following table default value00110011 bits 7:4 part 1 revision bits 3:0 part 2 revision 0000 1.0 0000 1.0 0001 1.1 0001 1.1 00101.200101.2 0011 1.3 0011 1.3 command ic_device_id (adh) format block read byte position3210 function mfr code id high byte id low byte reserved default value 49h d2h 22h 00h command ic_device_rev (aeh) format block read bit position 23:16 15:8 7:4 3:0 function firmware revision factory configuration chip foundry site ic revision default value n/a n/a n/a n/a
ISL68144 fn8888 rev. 3.00 page 45 of 48 feb 8, 2018 apply_settings (e7h) definition: instructs the controller to use new pmbus parameters. send 01h to this command after making one or more changes to certain pmbus threshold commands that require rescaling of operational values. the commands that require this are vout_transition_rate, vout_droop, vout_ov_fault_limit, vi n_ov_fault_limit, vin_uv_fault_limit, iin_oc_fault_limit, ton_rise, and toff_fall. paged or global: global data length in bytes: 2 data format: bit field type: write only default value: 01h restore_config (f2h) definition : identifies the configuration to be restored from nvm and lo ads the store?s settings into the device?s active memory. this command must be sent only wh ile the outputs are disabled. paged or global: global data length in bytes: 1 data format: bit field type: write only default value: n/a command restore_config (f2h) format bit field bit position76543210 access r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value n/a n/a n/a n/a n/a n/a n/a n/a bit number status bit name meaning 7:4 reserved reserved 3:0 config selected configuration to restore
ISL68144 fn8888 rev. 3.00 page 46 of 48 feb 8, 2018 revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please visit our website to make su re you have the latest revision. date revision change feb 8, 2018 fn8888.3 on page 41, changed the units for read_vout from ?v? to ?mv?. removed about intersil section. added current disclaimer. jul 7, 2017 fn8888.2 applied new header/footer. removed mention of the isl99226a part throughout the document. updated figures 2 and 3. updated ?enable (en0 and en1) input high level? spec on page 9, removed typical and added a min spec of 2.55v. added ?enable (en0 and en1) input low level? spec on page 9. on page 11, changed from ?scl, sda input high/low threshold? to ?scl, sda input high level?, removed typical, and added min spec of 1.55v. added ?scl, sda input low level? spec on page 11. on pages 26 through 35, updated the tables in th e pmbus command detail section for the following commands, changed from ?two?s complement integer? to ?unsigned integer?. - vout_command, vout_max, vout_margin_high, vout_margin_low, vout_transition_rate, vout_droop, vout_min, vout_ov_fault_limit, vout_uv_fault_limit, vin_ov_fault_limit, vin_uv_fault_limit, iin_oc_fault_limit, ton_delay, ton_rise, toff_delay, and toff_fall updated ?status_cml (7eh)? on page 40, changed bit 1 meaning to ?a communication fault other than the ones listed in this table has occurred.? updated ?read_pin (97h)? on page 43 from paged to global. feb 13, 2017 fn8888.1 updated description to reflect processor name change. corrected errors in rgnd0 and vsen0 pin descriptions. sep 28, 2016 fn8888.0 initial release
ISL68144 fn8888 rev. 3.00 page 47 of 48 feb 8, 2018 package outline drawing l40.5x5d 40 lead thin quad flat no-lead plastic package rev 0, 9/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.27mm from the terminal tip. dimension b applies to the metal lized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view jedec reference drawing: mo-220whhe-1 7. (4x) 0.15 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 5 6 5.00 a b 5.00 5.00 0.40 4x 3.60 36x 0.40 0.20 0.750 0.050 b 0.10 ma c package outline (40x 0.60) 0.00 min 0.2 ref 0.05 max c 0.10 // (40x 0.20) (36x 0.40) b 40x 0.4 0.1 3.65 3.65 6 4 for the most recent package outline drawing, see l40.5x5d .
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